1. Field
Example embodiments relate to a data output buffer circuit and a semiconductor device including the same (e.g. a data output buffer circuit which ensures signal quality irrespective of variation in operation voltage).
2. Description of Conventional Art
A semiconductor memory device may include a plurality of memory cells for retaining data. Data is stored in the memory cells during a write operation, and the data stored in the memory cells may be read during a read operation. The semiconductor memory device includes a data output buffer circuit, which outputs the read data to an external device.
Recently, data transmission between semiconductor memory devices is becoming increasingly high-speed. To accommodate this trend, signal amplitudes of transmissions flowing through an electronic system are reduced to permit data transmissions at high-speeds. In light of this approach, impedance matching may be employed to prevent amplitude variations of small amplitude data signals. In particular, matching the input impedance of a semiconductor memory device to the output impedance of the same reduces the variations. The input impedance of a semiconductor memory device is the impedance of the transmission path, which may include other semiconductor memory devices. The output impedance of the semiconductor memory device is equal to the impedance of the data output buffer circuit. During data transmission, if the impedance of the input and output are not matched accurately, the small amplitude data signal may become blunt, or be subject to over-shoot or under-shoot phenomena.
For such a reason, the output impedance of the data output buffer circuit of the semiconductor memory device must maintain a designated value and must be adjusted to match the impedance of the transmission path between semiconductor memory devices. However, the output impedance of the data output buffer circuit may vary according to the variation of an operation voltage (VDD).
One approach to maintaining matching impedances is by implementing a data-double-rate-3 (DDR3) memory device. Normally, the impedance of a data output buffer circuit tends to decrease as the operation voltage VDD decreases, and increase as the operation voltage VDD increases. Nevertheless, the data output buffer circuit of a DDR3 memory device may include a ZQ calibration circuit. A ZQ calibration circuit may lower the output impedance of the data output buffer circuit as the operation voltage VDD increases, and may raise the output impedance of the data output buffer circuit as the operation voltage VDD decreases. In other words, the ZQ calibration circuit adjusts the output impedance of the data output buffer circuit so as to be inversely proportional to the operation voltage VDD, which permits the operational voltage VDD to be maintained at a desired level. Accordingly, the ZQ calibration circuit maintains the output impedance of the data output buffer circuit at desired value so as to permit impedance matching with the impedance of the transmission path.
However, a ZQ calibration circuit may not achieve ideal impedance matching. Although output impedance Zout of the data output buffer circuit is maintained at a desired value through use of a ZQ calibration circuit, data output may still be influenced by the slew rate of an output signal. A slew rate is the slope of an output signal, which may vary under certain conditions. If the slew rate is too low, the variation width of access time increases and may result in signal quality deterioration. If the slew rate is too high, signal quality may also deteriorate due to bounce noise. Signal quality may be referred as “signal integrity.”
The slew rate of an output signal may be determined while designing a semiconductor memory device. Among the different design determinations, transistor size or resistance may indicate the degree of the signal slew rate. However, such a design determinations may still not accurately depict the slew rates, as the slew rate may vary according to the operation voltage VDD.
When the operation voltage VDD rises, the slew rate of the data output buffer circuit may increase. Likewise, when the operation voltages VDD lowers, the slew rate of the data output buffer circuit may decrease. In order to ensure a normal signal quality, minimum and maximum slew rate values have been suggested to ensure the signal quality of data output buffer circuit. Even still, signal quality may not be ensured if slew rate variations exceed either the maximum or minimum slew rate values.